bus_en=ignored, int_en=low, clk_count_mode=oscl
TWI Control Register
| clk_count_mode | 0 (oscl): scl clock high period count on oscl 1 (iscl): scl clock high period count on iscl |
| a_ack | Assert Acknowledge |
| int_flag | Interrupt Flag |
| m_stp | Master Mode Stop |
| m_sta | Master Mode Start |
| bus_en | TWI Bus Enable 0 (ignored): undefined 1 (respond): undefined |
| int_en | Interrupt Enable 0 (low): The interrupt line always low 1 (high): The interrupt line will go high when INT_FLAG is set |